1. Field of the Invention
The present invention relates to a Radio Frequency (RF) Mixer.
2. Description of the Related Art
Radio Frequency (RF) Mixers, also referred to as modulators, are used to up convert an IF input signal having an intermediate frequency to a desired output signal having an radio frequency (IF). These devices combine the IF input signal with a local oscillator (LO) signal at an LO frequency to produce an output signal with an RF equal to the sum or the difference of the LO and IF frequencies (LO+IF or LOxe2x88x92IF). Since this is an up conversion, the sum is the desired signal. Instead of up-converting, the RF mixer may also be used to down-convert a baseband analog. To down convert a signal, the RF signal is used as an input and the output comprises the IF signal.
FIG. 1 shows a known double-ended RF mixer (Gilbert cell) 10 for up conversion of an IF input signal including a first differential pair of transistors 20 including a first transistor Q1xe2x80x2 and a second transistor Q2xe2x80x2 and a second differential pair of transistors 22 including a third transistor Q3xe2x80x2 and a fourth transistor Q4xe2x80x2. Each of the first through the fourth transistors Q1xe2x80x2-Q4xe2x80x2 includes a base, a collector, and an emitter. A local oscillator (LO) is connected across the bases of the first differential pair of transistors 20 and the bases of the second differential pair of transistors 22. The emitters of the first differential transistor pair 20 are connected to the collector of a fifth transistor Q5xe2x80x2 and the emitters of the second differential transistor pair 22 are connected to the collector of a sixth transistor Q6xe2x80x2. The fifth and sixth transistors Q5xe2x80x2, Q6xe2x80x2 each have a base, a collector, and an emitter. A first current supply I1 is connected between the emitter of the fifth transistor Q5xe2x80x2 and an electrical ground and a second current supply I2 is connected between the emitter of the sixth transistor Q6xe2x80x2 and the electrical ground. The emitters of the fifth and sixth transmitters Q5xe2x80x2, Q6xe2x80x2 are connected to one another through an emitter degeneration resistor RD. The base of the fifth transistor Q5xe2x80x2 is connected to a first intermediate frequency signal terminal IF+ and the base of the sixth transistor Q6xe2x80x2 is connected to a second intermediate frequency terminal IFxe2x88x92. The first and second differential pair of transistors are cross coupled at their collectors to first and second radio frequency signal terminals RF+, RFxe2x88x92.
In the absence of an IF signal at IF+, IFxe2x88x92, the oscillations of the local oscillator causes the quiescent current of the first current supply I1 to commutate between the first and second transistors Q1xe2x80x2 and Q2xe2x80x2 and the quiescent current of the second current supply I2 to commutate between the third and fourth transistors Q3xe2x80x2 and Q4xe2x80x2. As IF+ and IFxe2x88x92 change, the current through the fifth and sixth transistors Q5xe2x80x2 and Q6xe2x80x2 is modulated. The output at the RF terminals comprises either a sum or a difference of the oscillator frequency and the IF frequency. However, the relationship between IIF+ and IQ5 and the relationship between IIFxe2x88x92 and IQ6 are non-linear. To improve linearity, high biasing currents are used. Furthermore, the emitter degeneration resistor RD connected between the emitters of the fifth and sixth transistors Q5xe2x80x2 and Q6xe2x80x2 is given a large value. These measures require large current consumption.
The present invention provides an RF mixer having linear characteristics and low power consumption.
According to an embodiment of the present invention, an RF mixer comprises a first differential transistor pair including first and second transistors and a second differential transistor pair including third and fourth transistors. Each of the first though fourth transistors has a base, a collector, and an emitter. The RF mixer includes a first stage input frequency differential transistor pair including fifth and sixth transistors. Each of the fifth and sixth transistors has a gate, a drain, and a source. The drain of the fifth transistor is connected to the emitters of the first and second transistors and the drain of the sixth transistor is connected to the emitters of the third and fourth transistors. The RF mixer further includes a second stage input frequency differential transistor pair including seventh and eighth transistors, each having a gate, a drain, and a source. The drain of the seventh transistor is connected to the source of the fifth transistor and the drain of the eighth transistor is connected to the source of the sixth transistor. A bias voltage circuit is connected to the gate of the fifth transistor and the gate of the sixth transistor. A bias current circuit is connected to the gate of the seventh transistor and connected to the gate of the eighth transistor. A local oscillator is connected between the bases of the first and second transistors and between the bases of the third and fourth transistors. An input frequency input may be connected between the gates of the first stage input frequency differential transistor pair and an inverted input frequency input may be connected between the gates of the second stage radio frequency differential transistor pair.
The voltage bias circuit comprises a constant voltage source connected to the gate of the fifth transistor via a first resistor and the gate of the sixth transistor via a second resistor. The current bias circuit comprises a constant current source connected to the gate of the seventh transistor via a third resistor and connected to the gate of the eighth transistor via a fourth transistor. The current bias circuit further comprises a ninth transistor having a gate, a drain and a source. The ninth transistor is operatively connected to the constant current source so that the constant current output from said constant current source is divided into four paths. The first path includes the junction between the drain of the ninth transistor and the source of the ninth transistor, the second path includes the junction between the gate of the ninth transistor and the source of the ninth transistor, the third path includes the third resistor and the junction between the gate of the seventh transistor and the source of the seventh transistor, and the fourth path includes the fourth resistor and the junction between the gate of the eighth transistor and the source of the eighth transistor.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.